Non-ECC dual channel shared2 DDR2 SDRAM system memory (533Mhz)
- ECC
- Error Correcting
- DDR
- transfers data on rising and falling edges of clock cycle
- DDR2
- transfers data 2x on rising and falling edge of clock cycle. Taken from Wikipedia article.
Chips
- DDR2-400: DDR-SDRAM memory chips specified to run at 100 MHz, I/O clock at 200 MHz
- DDR2-533: DDR-SDRAM memory chips specified to run at 133 MHz, I/O clock at 266 MHz
- DDR2-667: DDR-SDRAM memory chips specified to run at 166 MHz, I/O clock at 333 MHz
- DDR2-800: DDR-SDRAM memory chips specified to run at 200 MHz, I/O clock at 400 MHz
DDR2-xxx (or DDR-xxx) denotes effective clockspeed.
Sticks/Modules
- PC2-3200: DDR2-SDRAM memory stick specified to run at 200 MHz using DDR2-400 chips, 3.200 GB/s bandwidth
- PC2-4200: DDR2-SDRAM memory stick specified to run at 266 MHz using DDR2-533 chips, 4.267 GB/s bandwidth
- PC2-5300: DDR2-SDRAM memory stick specified to run at 333 MHz using DDR2-667 chips, 5.333 GB/s bandwidth
- PC2-6400: DDR2-SDRAM memory stick specified to run at 400 MHz using DDR2-800 chips, 6.400 GB/s bandwidth
PC2-xxxx (or PC-xxxx) denotes theoretical bandwidth (though it is often rounded up or down). Bandwidth is calculated by taking effective clockspeed and multiplying by eight. This is because DDR2 can transfer 64 bits of data each clock cycle, and since a byte is comprised of 8 bits, this equates to 8 bytes of data per clock cycle.